Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
Home   Personas   Investigación   Docencia   Doctorado   Publicaciones   Herramientas   Bolsa de Empleo   english version Tue 23-Jul-24 . 13:28

Mapa Web



Info Santander

Gestión BD

   Ficha completa
Título:Local Application of Simulation Directed for Exhaustive Coverage of Schedulings in SystemC Specifications
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:Proceedings of the Forum on specification and Design Languages, FDL'09, IEEE, 2009
Autores: Fernando Herrera
Eugenio Villar
Líneas: Diseño y verificación de sistemas embebidos HW/SW
Proyectos: IST 033511 ANDRES
Resumen:The production of input test benches for SystemC system-level specifications in SystemC has been efficiently covered by extensions like the SCV library and its commercial counterparts, which can be as effectively applied in Electronic System Level (ESL) as in RTL design. Other works have provided means to consider, for fixed input data, the different schedulings feasible in a valid execution, under the SystemC simulation semantics. These works provide an efficient exploration of such feasible schedulings by extracting and analyzing from the SystemC specification data and synchronization dependencies. However, in complex and heterogeneous specifications, there can be parts where such extraction and analysis become unfeasible. To overcome it, this paper proposes and enables the local application of simulation of Directed for Exhaustive Coverage of Schedulings or DEC simulation for those parts. The paper shows how these features, not currently provided by any SystemC simulator, have been integrated, validated and made available as an extension of the OSCI SystemC reference kernel. Acceso al trabajo.
© Copyright GIM (TEISA-UC)    ¤    Todos los derechos Reservados.    ¤    Términos LegalesE-Mail Webmaster