Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
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Título:Design-for-Test Method for High-Speed ADCs: Behavioral Description and Optimization
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS´11), Cottbus (Germany)
Autores: Yolanda Lechuga
Román Mozuelos
Mar Martínez
Salvador Bracho
Resumen:This paper presents a Design-for-Test (DfT) approach for folded analog to digital converters. A sensor circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of a defect can be detected. A fault evaluation is carried out on a behavioral model to compare the coverage of the proposed test approach with the one obtained from a functional test. Then, the analysis is moved to a transistor level implementation of the ADC to establish the threshold limits for the DfT circuit that maximize the fault coverage figure of the test approach.
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