Here you find the documentation on the GESE/UC methodology for modelling of embedded systems in UML/MARTE.
Introduction April 2014 A short introduction to the modelling methodology: views and modelling process Core Methodology May 2016 A detailed description on the capture of each modelling view
Design Activity Specific Documentation
On top of the core documentation, the following documentation explains the parts of the methodology oriented to cover specific aspects and features of interest for supporting ESL design activities:
Design Space Exploration May 2016 Modelling for single-source for Design Space Exploration (DSE) SW Synthesis for Heterogeneous Systems April 2015 Modelling for SW synthesis for heterogeneous targets Mixed Criticality Systems May 2016 Modelling of Mixed-Criticality systems (MCS) Schedulability Analysis April 2015 Modelling for Schedulability Analysis Distributed Embedded Systems October 2015 Network modelling for captruing distributed embedded systems
Moreover, research has been done to link UML/MARTE to other back-ends, e.g the ForSyDe-SystemC framework and the KisTA performance analysis tool. The last available documentation on its current status is given following:
|Interoperability with SDF Models||April 2015||Tech report on the interoperability of UML/MARTE and SDF models, used as base for the generation of ForSyDe-SystemC models from UML/MARTE|
|Scheduling policies, TDMA bus, KisTA||April 2015||Tech report on the extension of the UML/MARTE modelling for the description of models in UML/MARTE of predictable models with simple tasks mapped to local schedulers, whose scheduling policy can be configured and running on a TDMA bus platform. Used for prototype code generator targeting KisTA performance analysis models|