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15 December, 2017

This site presents a demo of the possibilities of the UML/MARTE framework. For such purpose, links to the tools required for a small design flow including steps for UML/MARTE modeling, code generation and early simulation are listed below. Additionally, some UML/MODEL examples are provided, to check the flow.

Complete instance of Eclipse+Acceleo+CONTREP
Links are protected by a keyword. Please contact with Eugenio Villar to request it.

Link Date Short Description
 Eclipse Contrep 64b 02-03-2017 complete instance of Eclipse+Acceleo+CONTREP (Linux 64b)
 Eclipse Contrep 32b 02-03-2017 complete instance of Eclipse+Acceleo+CONTREP (Linux 32b)
 Essyn DCGen 02-03-2017 Essyn DCGen
 VIPPE v2.3 18-10-2016 VIPPE 2.3

Examples

Example name
Description
 prueba_1ms_1rtos Two components each with an internal periodical function. One component with an initialization function. One component implements and provides a service required by the other component. Both , components mapped to one memory space, in turn mapped to the same operative system.
 prueba_2ms_1rtos As prueba_1ms_rtos example, but the two components are mapped to different memory spaces. Both memory spaces are mapped to the same operative system.
 prueba_2ms_2rtos_shared_reg As prueba_2ms_1rtos, but the two memory spaces are mapped to different RTOS, in turn running on different processors, buses, and thus memory maps. As the communication traverses two memory spaces, no channel based communication is used in this case, but it is based on a shared memory directly mapped for both sides. (Generation and run of simulation model supported and relying on the modeling of directly mapped physical memory of VIPPE. Generation of native model requires code adaptation).
 prueba_2ms_2rtos_ppunit As prueba_2ms_2rtos_shared_reg, but the shared memory access traversing 2 RTOS and 2 buses (memory maps) is encapsulated and made explicit in the UML/MARTE model through 2 PpUnits (one for each memory space). (Generation and run of simulation model supported and relying on the modeling of directly mapped physical memory of VIPPE. Generation of native model requires code adaptation).
prueba_2ms_2rtos_socket_com As prueba_2ms_1rtos, but the two memory spaces are mapped to different RTOS, in turn running on different processors., buses, and this memory maps . In this case, the channel based communication is preserved, but by specifying a socket based communication. (Code generation is supported. VIPPE support of socket on-goin at the time this example was uploaded).