Virtual Platform Parallel performance Evaluation


VIPPE provides a unique combination of features for a virtual platform base design.

Fast simulation speed

VIPPE is based on native simulation, a fast simulation technology. VIPPE brakes the limitation of other simulation technologies to exploit underlying parallelism of host platforms by enabling thread based parallel native simulation.

Estimation of extra functional properties

VIPPE enables the estimation of the performance by reporting a rich set of performance metrics. VIPPE provides time, power and energy metrics. It includes global metrics and metrics related to application and platform elements. Breakdowns per platform elements (processors, buses, memories) and information on metrics like cache performance, are provided to let the early analysis of performance bottlenecks.

Easy and flexible platform model

VIPPE has been designed as an optimum simulation-based performance assessment technology for Design Space Exploration (DSE). Underlying breaking edge techniques are oriented to provides good accuracy (e.g., to enable DSE) while maximizing simulation speed. Configuring a different platform is a matter of changing a simple XML file or passing parameter value to a run command, to avoid the re-factoring or recompilation of the input model.

Other features

VIPPE provides additional features for an enhanced platform modelling, e.g. possibility of co-simulation with SystemC, and analysis, e.g. VIPPE has a graphical interface for run-time reports, and it supports the Multicube interface for automated DSE. VIPPE is being used by several industrial and academic partners in different European projects, and through close collaboration with GIM/UC.


Virtual Platform Parallel performance Evaluation
Design of embedded systems requires solutions for evaluating the system before creating the real prototype.

Commonly, embedded system performance is evaluated in advance through slow Instruction Set Simulators. A recent technology like binary-translation provides a faster alternative, capable to provide instruction accurate figures and model low-level details, which allows cross-development on top of the virtual platforms relying on this technology. However, early evaluations for design space esploration come before deciding the platform architecture (how many and which many processors, which interconnect, the memory hierchy and configuration, etc) and before targeting the code (what has to be executed on one processor or another, what to move to one accelerator or to HW). All those decisions compose a potentially hughe design space which demands even faster assessement speed. VIPPE relies on a cutting-edge technology called parallelized native simulation. Native simulation is a technology capable to outperform binary translation in simulation speed and to get yet estimates on time, energy and power sufficiently accurate for enabling design decisions. Moreover, VIPPE enables easy and flexible creation of platform models, getting rid from SW cross-development details, and the possibility to connect the VIPPE model to an exploration tool for an automated DSE environment. Moreover, parallelized native simulation enables VIPPE to exploit the underling parallelism of current host development platfoms.


VIPPE is a complex tool infrastructure which integrates many techniques and parts, which have been progressively developped thanks to the funding of different projects and entities.


In CONTREX, accurate performance analysis (timing, energy and power) considering platform elements is enabled. Interfaces for co-simulation with SystemC and for automated Design Space Exploration, and a component-based UML-MARTE front-end is provided too.


In the CRAFTERS project, the seminal idea and the development of thread-based parallelized native simulation kernel was developped. In this project, a easy-to-use UML/MARTE front-end is provided too.


In HARP, further polishing of the VIPPE kernel was done, and main contributions are related to adding APIs or the user code, e.g. OpenMP. Moreover, a hardware estimation part was added, and other relevant features as the GUI for analysis of thread scheduling.

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