Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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 Métodos de test para Convertidores ADC de Alta Velocidad
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Title:Métodos de test para Convertidores ADC de Alta Velocidad
Budget:0€ Years, begin:2006  end:2007 
Director:Salvador Bracho 
R&D Lines:  
Staff: Salvador Bracho
Mar Martínez
Miguel Angel Allende
Román Mozuelos
Yolanda Lechuga
Description:The flash and folded ADC are good solutions to have a high speed analog-to-digital conversion and there are many works about these converters to improve its resolution, at the same time that increasing many other performances.
Carrying out tests of flash and folded analog-to-digital converters requires better and better methods, among which the incorporation of Dft and BIST designs should be highlighted, where according to the 2005 report of the ITRS, to reach the necessary efficiency in these DfT techniques in the test procedure after manufacture, it is necessary to carry out greater research on them.
This project proposes a one-year study, at behavioral level, of the impact of the possible test structures used to carry out a DfT or BIST testable design, in different high-velocity analog-digital converter architectures.
Naturally, to do this we must study the BIST and testable design structures in depth to obtain their maximum performance in the test process. Then, we propose developing a DfT approach for carrying out a structural test of the doubled analog-digital converters.
Finally, in one of the initial design steps of these testable analog-to-digital converters we will confront the problem of simulation of the most critical blocks, as well as their modification for incorporation of test structures.
In this way, we will obtain valid information for the designers of converters where the advantages will be highlighted in terms of test/performance, design difficulty, power, etc.
Later in a subsequent project, the design and development of demonstrators can be approached within the state-of-the-art technologies that are valid for these circuits, which we be the ADC necessary for validation of the test methods proposed.
In this way decisions can be taken jointly by GIM/UC CNM/IMSE about which will be the high-velocity ADC architectures to be developed in the applications currently of greatest interest to the IMSE and where the application of DfT or BIST techniques will be most effective.  

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