Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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GIM>Research>project>PAVES. TEC2008-04107...
PROJECT:
 PAVES. TEC2008-04107. ANALISIS DE PRESTACIONES Y VERIFICACION DE SISTEMAS EMBEBIDOS MULTIPROCESADORES
   
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Title:PAVES. TEC2008-04107. ANALISIS DE PRESTACIONES Y VERIFICACION DE SISTEMAS EMBEBIDOS MULTIPROCESADORES
Acronym: 
Payer:Ministerio de Ciencia e Innovacion 
Partners: 
Budget:108000€ Years, begin:2009  end:2011 
Director:Pablo Pedro Sánchez 
R&D Lines:  
Staff: Pablo Pedro Sánchez
Eugenio Villar
Iñigo Ugarte
Héctor Posadas
Description:The goal of the project is to deal with some of the new challenges that Model-Driven Architecture methodologies (MDA) propose for Multi-Processor Embedded System design, mainly aspects focusing on performance analysis and system-level verification of models described in SystemC. The proposal emerges from the experience acquired by the research team in the TEC2005-2008 EMVITE (“Validation and Implementation Technologies in SW/HW Embedded System Platforms”) project, as long as from the interaction with different companies, carried out in national (CENIT) and international (FP7, MEDEA+ and ITEA) projects. This experience has allowed the research team to identify new working areas that have produced a large interest in both research and industrial application areas. These new working areas can be summarized in 4 groups:

1.- Definition of techniques that guarantee that the System-Level descriptions in SystemC are equivalent to the specifications previously modeled following MARTE (future standard extension of UML2 for embedded systems) or AADL (Architecture Analysis & Design Language) paradigms.

2.- Development of methodologies to estimate power consumption and execution times. For a unique code, these estimators will be capable of determining the performance of the described module, for both mapping possibilities: hardware implementation and software execution (in a processor of the system).

3.- Exploration of semi-formal verification techniques capable of checking the model behavior as well as its non functional parameters (such as timing constraints).

4.- Definition of a design flow, acceptable by the project observer and promoter entities, which provides the capabilities required to design, implement and validate physical prototypes of multi-processor platforms. To be able to transfer these technologies to small or medium companies, it is necessary to demonstrate their practical efficiency with real prototypes that the company can test and evaluate.
 

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