Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Técnica para simulación de fallos en un entorno VHDL
Type:National Conference
Where:Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza
Date:1995-11
Authors: I. Hidalgo
Pablo Pedro Sánchez
R&D Lines: Test methods of digital and mixed integrated circuits
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