Microelectronics Engineering Group

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Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Mixing Synchronous Reactive and Untimed MoCs in SystemC
Type:Book chapter
Where:"Applications of Specification and Design Languages for SoCs", A. Vachoux (Ed.), CHDL Series, Springer
Authors: Fernando Herrera
Eugenio Villar
R&D Lines: Design and verification of HW/SW embedded systems
Projects: Metodologías de especificación, análisis de prestaciones y verificación d...
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Abstract:This work is in the context of the development of a heterogeneous system-level specification methodology based on SystemC.
The methodology is able to support untimed MoCs (such as PN, KPN and CSP) and MoCs with a more detailed handling of time, such as the synchronous reactive (SR) MoC. In this paper, previous work on untimed-untimed interfaces is extended with the connection between untimed MoCs and the SR MoC. That connection involves the intersection of different MoC restrictions in the time domain. The way in which the untimed-SR interface specifies how the untimed events map onto the SR time domain is shown. These general concepts are reflected later in the SystemC untimed-SR interfaces, consisting of border processes and channels. The incompatibilities between time restrictions provoked or transmitted by the connection are also shown, as well as the way these are detected in SystemC.
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