Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systems
Type:International Conference
Where:ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE'05). Italy
Date:2005-07
Authors: Iñigo Ugarte
Pablo Pedro Sánchez
R&D Lines:
Projects:
ISBN:0-7803-9227-2
PDF File:
Abstract:As the latest version of the International Technology
Roadmap for Semiconductor (ITRS) highlights,
verification has become the dominant cost of the
electronic system design process. Although advances
in formal methods have improved some aspects of the
task, software simulation remains the primary method
of functional verification.
Traditionally, heuristic coverage metrics have been
used to evaluate the simulation-based verification
process. This coverage-based approach has a very
serious disadvantage: the metrics have no formal
meaning and so there is no direct correlation between
classes of bugs and coverage metrics.
The main goal of this paper is to explore methods that
provide a formal meaning to branch coverage with
random test benches. The methods are based on
polynomial models of the system under verification
and they are independent of a particular fault model.
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