| PUBLICATION |
| Full record |
|Title:||Embedded software execution time estimation at different abstraction levels|
|Where:||XXV Conference on Design of Circuits and Integrated Systems, DCIS'10|
Pablo Pedro Sánchez
Design and verification of HW/SW embedded systems
|Abstract:||The increasing popularity of portable devices has driven a big effort in analyzing and optimizing software execution time on embedded systems. Additionally, most of the system's functionality is implemented in software which enables high levels of flexibility and re-configurability. This software is executed in an everyday more complex platform that is evolving to high-performance Multiprocessor System on Chip (MPSoC). |
Current design methodologies need early estimations to guide the design process but this growing complexity has made the process far from easy. Many techniques have been proposed to provide fast software execution estimations. Methodologies based on Instruction Set Simulator (ISS) use traces of instructions at ASM level providing accurate results with relatively low simulation time (typically x100 over register transfer level simulations). However, an additional speed-up is needed in order to evaluate real embedded applications. Other techniques are based on clusters of instructions instead of single ones, providing less accurate results at expense of faster simulations. An interesting way to extract these blocks is to characterize every element of the grammar of a high-level software language. This technique is called “Source Code Analysis” and works at source level. Low-level details are not considered in this technique so faster simulations can be performed with a little accuracy penalty.
This paper presents four approaches to time estimation at different abstraction levels and compares them in terms of accuracy and execution time. Some techniques are introduced to speed up the simulation while providing accurate results.