Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Automatic Generation of SystemC SMP Models for HW/SW Co-Simulation
Type:International Conference
Where:XXV Conference on Design of Circuits and Integrated Systems, DCIS'10
Date:2010-11
Authors: Patricia Botella
Pablo Pedro Sánchez
Héctor Posadas
R&D Lines: Design and verification of HW/SW embedded systems
Projects: Artemis SCALOPES
ISBN:978-84-693-73934
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Abstract:As the complexity of system-on-chip (SoC) design is increasing rapidly, design verification has been attracting more attention in recent years. Nowadays multiprocessor system-on-chips (MPSoCs) are becoming more commonly used in embedded systems and most of them have symmetric multiprocessor (SMP) architectures. In these architectures, two or more identical processors are connected to a single shared main memory and they are controlled by a single OS instance. Developing software for multiprocessor architectures is known to be complex and tedious, as it requires a combination of high-level programming environments with low level software design. Several verification techniques have been introduced to validate MPSoC-based embedded systems during the design process such as instruction set simulation (ISS), software emulation and native (host compiled) simulation.
In this paper a methodology for generating a SystemC SMP model for native simulation is proposed. Native simulation is faster and less complex than ISS because the software source-code is directly compiled and annotated in the simulation host computer. This provides efficient and precise simulation models at the highest abstraction levels that are required to perform early design validations and architecture explorations. This work is based on SCoPE, a HW/SW native simulator.
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