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| PUBLICATION |
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| Full record |
| Title: | Fast Data-Cache Modeling for Native Co-Simulation
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| Type: | International Conference |
| Where: | Asia and South Pacific Design Automation Conference, ASP-DAC 2011 |
| Date: | 2011-01 |
| Authors: |
Héctor Posadas
Luis Diaz
Eugenio Villar
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| R&D Lines: |
Design and verification of HW/SW embedded systems
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| Projects: |
Artemis SCALOPES
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| ISBN: | 978-1-4244-75148 |
| PDF File: |
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| Abstract: | Efficient design of large multiprocessor embedded systems requires fast, early performance modeling techniques. Native co-simulation has been proposed as a fast solution for evaluating systems in early design steps.
Annotated SW execution can be performed in conjunction with a virtual model of the HW platform to generate a complete system simulation. To obtain sufficiently accurate performance estimations, the effect of all the system components, as processor caches, must be considered. ISS-based cache models slow down the simulation speed, greatly reducing the efficiency of native-based co-simulations. To solve the problem, cache modeling techniques for fast native co-simulation have been proposed, but only considering instruction-caches. In this paper, a fast technique for data-cache modeling is presented, together with the instrumentation required for its application in native execution. The model allows the designer to obtain cache hit/miss rate estimations with a speed-up of two orders of magnitude with respect to ISS. Miss rate estimation error remains below 5% for representative examples.
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