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|A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design
|ASP Journal on Low-Power Electronics (JOLPE): Special Issue on Low Power Design and Verification Techniques
Pablo Pedro Sánchez
Design and verification of HW/SW embedded systems
|In MPSoC design, the analysis of chip temperature is becoming increasingly important due to its impact on system reliability, power consumption and cost. In this paper, we propose a complete framework based on native simulation to early estimate the power consumption and the thermal flow in MPSoC systems. Native simulation allows fast modelling and simulation of the embedded software running on a concrete platform in close interaction with all the platform components. The activity of each component is monitored by using high-level models, being possible to estimate the power consumed. The power figures feed a high-level MPSoC thermal model which supplies chip temperatures estimations. At the same time, advanced techniques to manage power and temperature have been modeled. Thus, the proposed framework allows detecting power and thermal hot spots in the first stages of the design flow, allowing the exploration of different alternatives to address these problems. The framework has been validated by comparing the results provided with an Instruction Set Simulator. The results show around an x% percent of error in the estimations, while simulation time is speeded up x orders of magnitude. Different examples have been developed to demonstrate the capabilities of proposed methodology on a variety of use cases..