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|Deliverable D5.4 the FP7-216807 SATURN Project
Design and verification of HW/SW embedded systems
FP7 216807 SATURN
This deliverable is part of the SATURN project which is a European initiative financed under the 7th FP and addresses SysML based modelling, architecture exploration, simulation and synthesis. SATURN’s goal is to bridge the current gap between modelling and verification/synthesis in UML based designs of Embedded Systems that are equally composed of HW and SW.
This document presents the FPGA designs coming out the case studies by INTRACOM and T3S. It details the experience of these two partners when trying to use the SATURN tools, and how it differs from the use of standard tools.
Aim of the deliverable
This report presents SysML and SATURN models for each case study, and more detailed models for designing part of each system’s functionality and the implementation platform.
The goal of this deliverable will be the identification of advantages and disadvantages of the second increment of the SATURN methodology and tools and therefore the evaluation of the project’s achievements.