Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Definition of tool interfaces and integrated design flow
Type:Report, Study or Opinion by order
Where:Deliverable D1.2 of the FP7 Pharaon Project
Date:2012-06
Authors: F. Colas-Bigey
A. Terechko
Héctor Posadas
Eugenio Villar
Pablo Peñil
F. Broekaert
C. Couvreur
M. Bourdelles
S. Li
L. Lavagno
A. Cohen
R&D Lines: Design and verification of HW/SW embedded systems
Projects: FP7 288307 PHARAON
ISBN:
PDF File:
Abstract:One objective of the PHARAON project is to define a methodology to go from high level modeling towards implementation of code onto a parallel architecture. To achieve this implementation, the code will be successively transformed and go through a set of tools that
will offer the possibility to:
· Find the most adequate parallel architecture for the application
· Introduce parallelism in the application through the use of OpenMP
· Evaluate timing and power performances of the system
· Generate the code to be embedded onto the physical platform
· Add low power directives to the application and take benefit from the low power framework implemented on the platform

The complete PHARAON design flow is therefore dense and communications between the different tools composing the framework have to be extensively detailed. This document depicts the different steps of the flow and details the nature of information exchanged
between the different tools.
The intent of this document is to specify interactions between these tools and highlight automatic or manual modifications at each step. It has to be noticed that the inner structures of tools are not detailed in this document since they will be depicted in WP2 and WP3 deliveries.
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