Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Formal Support for Untimed MARTE-SystemC Interoperability
Type:Book chapter
Where:T. Kazmierski & A. Morawiec (Eds.): "Systems Specification and Design Languages", Lecture Notes in Electrical Engineering, V.106, Springer
Authors: Pablo Peñil
Fernando Herrera
Eugenio Villar
R&D Lines: Design and verification of HW/SW embedded systems
Projects: FP7 IP 247999 COMPLEX
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Abstract:Model-Driven Architecture (MDA) and Electronic System Level (ESL) design are key approaches for succeeding in the specification and design of current embedded systems, which are increasingly complex and heterogeneous. MARTE is the most advanced UML profile for abstract specification of real-time embedded systems in the MDA context, while SystemC is the language most widely adopted by the ESL design community. Nevertheless, SystemC lacks well defined formal semantics for abstract specification, specifically for untimed models. This paper tackles this problem by providing the fundamentals of a framework which enables the analysis of the MARTE model and the corresponding SystemC specification under a formal meta-model. Based on this formal meta-model, formal support for a consistent and synergistic link between MARTE and SystemC is provided. This support is based on ForSyDe. The ForSyDe formalism is used as a formal framework for untimed SystemC models and to reflect the abstract execution semantics of both the MARTE model and its corresponding SystemC executable specification. Thus, the conditions for the SystemC specification to correspond to its formal meta-model are defined. The concepts introduced are shown through the specification of an essential part of a video decoder.
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