Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
Home   Personas   Investigación   Docencia   Doctorado   Publicaciones   Herramientas   Bolsa de Empleo   english version Mon 17-Jun-19 . 23:47



Mapa Web


Localización

Noticias

Info Santander



Gestión BD

GIM>Investigación>Publicación
   PUBLICACION
 
   Ficha completa
Título:Obtaining Memory Address Traces from Native Co-Simulation for Data Cache Modeling in SystemC
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:XXV Conference on Design of Circuits and Integrated Systems, DCIS'10
Fecha:2010-11
Autores: Luis Diaz
Héctor Posadas
Eugenio Villar
Líneas: Diseño de sistemas embebidos HW/SW
Proyectos: Artemis SCALOPES
ISBN:978-84-693-73934
Fichero:
Resumen:Native co-simulation is a fast solution for system modeling at early design steps. In this technique, the SW code is annotated with time information from the target processor and, then, it is executed in the workstation combined with a time-approximate HW platform model. This technique allows to simulate systems considering timing effects while simulation speed is maintained close to functional execution. Thus, in early design steps performance estimations can be obtained fast enough to explore the entire design spaces in reduced times. To obtain sufficiently accurate performance estimations, the effect of all the system components must be considered. Among them, processor caches are really important, as they have a strong impact on the overall system performance. However, no techniques for data cache modeling in native-based co-simulation have been proposed. Common cache modeling techniques start from memory access traces, howeve this information cannot be efficiently obtained from a native execution. As a consequence, new solutions are required. In this paper, it is proposed a technique for obtaining data address from the workstation for modeling a data cache. This model allows the designer to obtain cache hit/miss rate estimations. Miss rate estimation error remains below 4% in representatives codes.
Paper
© Copyright GIM (TEISA-UC)    ¤    Todos los derechos Reservados.    ¤    Términos LegalesE-Mail Webmaster