Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
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Título:UML/MARTE methodology for high-level system estimation and optimal synthesis
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:MeCoES - Metamodeling and Code Generation for Embedded Systems, ESWeek 2012
Fecha:2012-10
Autores: Héctor Posadas
Pablo Peñil
Alejandro Nicolás
Eugenio Villar
Líneas: Diseño y verificación de sistemas embebidos HW/SW
Proyectos: FP7 288307 PHARAON
ISBN:
Fichero:ver fichero
Resumen:Design of embedded systems is facing the challenge of their growing complexity and strict performance requirements. Model-driven design solutions are very common in this context, where the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. During the design process, several specification alternatives can be considered; specifically, the HW/SW platform, concurrent application structure, application allocation into HW/SW platform resources, etc. The exploration of these design alternatives enables a set of performance estimations to be obtained in order to choose the optimal specification, facilitating system implementation and minimizing designer effort. The paper proposes an UML/MARTE methodology the enables automatic estimation of the system to be implemented. Once the optimal system specification has been defined, the proposed UML/MARTE methodology enables the final system to be implemented through an automatic synthesis process.


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