Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:System specification methodology using MARTE and Stateflow
Type:Report, Study or Opinion by order
Where:Deliverable D2.1.1 of the COMPLEX project.
Authors: Francisco Ferrero (GMV)
R. Valencia (GMV)
Fernando Herrera
Eugenio Villar
L. Lavagno
D. Quaglia
R&D Lines: Embedded Systems Specification
Projects: FP7 IP 247999 COMPLEX
PDF File:
Abstract:This documents summarizes the first results of task 2.1 of COMPLEX project, by defining a system-level specification methodology by means of two different modelling languages, UML/MARTE and Stateflow, identifying all those features of the system-level modelling language relevant for the characterization of the system functional and non-functional properties and the estimation of system performance. In order to develop an executable model of the system, it is necessary to transform the high-level models into an executable, SystemC specification, which enables fast functional validation, and performance estimations. This way, such SystemC specification will make feasible in the COMPLEX design flow, the optimization of the system architecture after a design space exploration (DSE) phase with a reasonable bound in time. This document addresses this transformation and provides a first insight on the implementation of the tools required for carrying out the task.
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