Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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GIM>Research>Behavioral Test Synt...
 Behavioral Test Synthesis
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Pablo Pedro Sánchez (Responsible for this Research Line)
Víctor Fernández
As a consequence of the activity in behavioral synthesis, a parallel activity in behavioral test synthesis was carried out. The objective was to minimize the circuit generated during behavioral synthesis taking into account testability criteria in addition to cost and speed. Two different cases were explored. On the one hand, using partial scan [FSV95][FSV95a][FePa96] and, on the other, without any design for testability facility [FSV93][FSV94][FePa96a][FePa97][FePa98][FePa98a][Fe98]. This knowledge was applied in VHDL design for test [GVB95] and in fault modeling and simulation with VHDL [FSG94][BHF95][EBO95][EOS95][BSV96]. As it will be described later, this know-how is now being exploited in verification of embedded systems.
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