Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Automatic Communication Modeling for Early Exploration of HW/SW Allocation Based on Native Co-simulation
Type:International Conference
Where:XXVI Conference on Design of Circuits and Integrated Systems, DCIS'11
Authors: Héctor Posadas
Eugenio Villar
R&D Lines: Design and verification of HW/SW embedded systems
Projects: FP7 IP 247999 COMPLEX
PDF File:see file
Abstract:During architectural mapping, the exploration of all possible allocations requires a huge amount of performance analysis evaluations. As a consequence, it is mandatory to find new techniques able to provide the design-space exploration (DSE) tool with fast, accurate enough performance metrics. State-of-the-art techniques require the complete SW stack to be executed in each processing node. Therefore, DSE has to be postponed to the point where the complete SW stack including the HW-dependent SW has been developed. This paper proposes an alternative solution capable of modeling initial, functional SW code, evaluating the communication impact derived from multiple architectural mappings without requiring any communication refinement.
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