Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Automatic synthesis from UML/MARTE models using channel semantics
Type:International Conference
Where:International Workshop on Model-Based Arquitecting and Construction of Embedded Systems, ACES-MB 2012, doi: 10.1145/2432631.2432640
Date:2012-09
Authors: Pablo Peñil
Héctor Posadas
Alejandro Nicolás
Eugenio Villar
R&D Lines: Design and verification of HW/SW embedded systems
Projects: FP7 288307 PHARAON
ISBN:1-58113-000-0010
PDF File:see file
Abstract:Model-driven design is very common nowadays. In this context, the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. This profile enables the functional and non-functional details of the system to be modeled together. Regarding non-functional details, the profile allows certain real-time constraints to be imposed when describing the system concurrency, in order to ensure predictability. However, these constraints also limit the modeling flexibility required to evaluate different design solutions when optimizing system performance. This paper proposes a solution for automatically synthesizing the resulting models, combining new communication semantics with standards UML/MARTE real-time management features. The UML/MARTE approach presented in this paper enables concurrency and synchronization effects to be modeled at communication points, making system exploration and implementation easier.
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