Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Automatic synthesis of Embedded SW Communications from UML/MARTE models supporting memory-space separation
Type:International Conference
Where:XXVII Conference on Design of Circuits and Integrated Systems, DCIS'12
Date:2012-11
Authors: Héctor Posadas
Pablo Peñil
Alejandro Nicolás
Eugenio Villar
R&D Lines: Design and verification of HW/SW embedded systems
Projects: FP7 288307 PHARAON
ISBN:978-2-95174611-4
PDF File:see file
Abstract:The proposed approach presents a solution for automatically synthesizing the SW code of complex embedded systems from a model driven system specification. The solution is oriented to enable easy exploration and design of different allocation of SW components in heterogeneous platform, minimizing designer effort. The system is initially described following the UML/MARTE standard. Applying this standard, the system is modeled, describing its components, interfaces and communication links, the system memory spaces, the
resource allocations and the HW architecture. From that information, a SW infrastructure containing the communication infrastructure is generated ad-hoc for the system depending on the HW architecture and the resource allocations evaluated. As a result, the infrastructure
synthesized is more specific and simple than previous approaches using solutions such as CORBA or RMI. The consequent communication overhead reduction can result in an important advantage for system performance.
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