Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:VIPPE: Parallel simulation and performance analysis of complex embedded systems
Type:International Conference
Where:HiPPES4CogApp: High Performance, Predictable Embedded Systems for Cognitive Application
Authors: Luis Diaz
Eduardo González
Eugenio Villar
Pablo Pedro Sánchez
R&D Lines: Design and verification of HW/SW embedded systems
Projects: Artemis 332913 COPCAMS – Cognitive & Perceptive CAMeraS
PDF File:see file
Abstract:Native simulation technologies has shown its capability to generate virtual platforms at the beginning of the design process, thus allowing early detection of bugs and optimization of the application SW on a specific executive platform. As with any Discrete-Event simulation technique, native simulation finds problems when trying to take advantage of the multi-processing capabilities of current host workstations where the simulation will be executed. Ensuring deterministic behavior implies synchronizing all the parallel threads. As a consequence, the number of cores that can be active during simulation is dramatically reduced and the simulation time increased. The paper proposes a native simulation framework, called VIPPE, which minimizes the synchronization overhead thus taking advantage of the multi-processing capabilities of the host platform. The approach has been evaluated with representative video processing algorithms showing the suitability of the simulation technique to cognitive and perceptive camera systems.
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