Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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GIM>Research>Previous activities ...
 Previous activities in VHDL design
   Select these links to see PROJECTS or PUBLICATIONS within this research line
Eugenio Villar (Responsible for this Research Line)
Miguel Angel Allende
Víctor Fernández
Pablo Pedro Sánchez
The experience of the group in Hardware Description Languages (HDLs) started in 1982 with the study and application of languages like AHPL, DDL and ISPS in the design and verification of electronic circuits. VHDL is the HDL used in the group since the beginning of the 90’s.
Behavioral Test Synthesis
As a consequence of the activity in behavioral synthesis, a parallel activity in behavioral test synthesis was carried out. The objective was to minimize the circuit generated during behavioral synthesis taking into account testability criteria in addition to cost and speed. Two different cases were explored. On the on... [+]
Synthesis application of VHDL
Synthesis application of VHDL requires the definition of several syntactical restrictions and description styles. During the 90’s, the use of VHDL in RT synthesis was a very active, international research area. Our participation to the ESPRIT 8370 ESIP [PRO93] pro... [+]
Behavioral Synthesis
The activity in embedded systems design follows a previous experience in behavioral synthesis started in 1990. This research topic was funded by several CICYT projects and led to the development of the PSAL2 and FIRES behavioral synthesis tools acquired by companies and research centers such as <... [+]
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