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| PROJECT: |
| ||Tecnologías de Verificación e Implementación en plataforma de
Sistemas Embebidos SW/HW |
| Select this link to see PUBLICATIONS within this project |
|Title:||Tecnologías de Verificación e Implementación en plataforma de
Sistemas Embebidos SW/HW|
|Payer:||MCYT TIC-2005-03301 |
|Partners:||Enwesa, TTI, Alcatel y Tekniker |
|Director:||Pablo Pedro Sánchez |
Design and verification of HW/SW embedded systems
Pablo Pedro Sánchez
Jesús Angel Adámez
|Description:||This project continues research lines that were started by the TIC 2002-2005 EVASEC project (Specification methodologies, performance analysis and verification of embedded systems described in SystemC) and take into account the experience in participating in MEDEA+ and ITEA projects. The goal is to research and to develop techniques that allow improving the|
embedded system design process. These techniques have a high research and industrial interest. The goals of the project can be classified into 3 main areas:
1.- SystemC specification of platform specific models. Every time more software development companies use UML-based model-driven specification techniques. In order to implement
these models on SystemC, new specification methodologies have to be defined. Additionally, the refinement process from UML to SystemC needs precise performance estimations that have to be obtained from the SystemC performance analysis.
2.- Verification is the main bottleneck of the design process. There is a need of new techniques that can handle the verification of complex designs with concurrent tasks.
3.- One of the limitations, that we have had in order to disseminate these methodologies to SME, is the need of a design flow that generates physical prototypes, that allow validating the approach. Thus, the third research line includes the design flow definition, prototype development and, a new aspect, SystemVerilog-based hardware design flow.