Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Level-0 VHDL synthesis syntax and semantics
Type:Report, Study or Opinion by order
Where:CENELEC TC117 ENV
Date:1995-12
Authors: Eugenio Villar
R&D Lines: Design and verification of HW/SW embedded systems
Projects: ESPRIT 8370 ESIP
ISBN:
PDF File:
Abstract:
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