| PUBLICATION |
| Full record |
|Title:||Experimental Analysis of Transient Current Test Based on dIDD Variations in S2I Memory Cells|
|Where:||XIX Conference on Design of Circuits and Integrated Systems (DCIS2004). Bordeaux (France)|
Miguel Angel Allende
Test methods of digital and mixed integrated circuits
Técnicas de Test para Circuitos Mixtos, Analógicos-Digitales. Aplicación ...
|Abstract:||The current variations, δIDD, appearing in the memory cells of SI circuits in the presence of faults, give rise to changes in the overall dynamic supply current, IDDT, which are analyzed in the test methods based on this IDDT current.|
The capability of propagation of the effects of the faults injected inside the circuit can be considered, and we will call it as fault reflection.
Basing on this fault reflection mechanism, a new test method that directly analyzes the current variations, δIDD, appearing in one of the memory cells that constitute the SI circuit, has been developed.
This test method has the advantage of avoiding the losses of information appearing in the integration of the IDDX signal, which can mask the effects of the faults.
We have designed and built, in AMS 0.6 technology, a benchmark circuit based on a switched-current algorithmic A/D Converter topology to establish the fault coverage obtained with this new test method, by real measurements; and conclusions have been extracted.