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Title:	VHDL synthesis description portability: The need for Level-x synthesis subsets
Type:	International Paper
Where:	Journal of System Architecture 42, North-Holland, pp 105-116
Date:	1996-01
Authors:	M. Selz W. Ecker Eugenio Villar
R&D Lines:	Design and verification of electronic systems for communications
Projects:
ISBN:	1383-7621
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Abstract:


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