Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:Ravenscar Computational Model compliant AADL Simulation on LEON2
Type:International Conference
Where:International Symposium on Information System and Software Engineering, ISSE 2011
Authors: Roberto Varona
Eugenio Villar
A-I. Rodríguez (GMV)
R&D Lines: Design and verification of HW/SW embedded systems
Projects: HWSWCO
PDF File:see file
Abstract:AADL has been proposed for designing and analyzing SW and HW architectures for real-time mission-critical embedded systems. Although the Behavioral Annex improves its simulation semantics, AADL is a language for analyzing architectures and not for simulating them.
AADS-T is an AADL simulation tool that supports the performance analysis of the AADL specification throughout the refinement process from the initial system architecture until the complete, detailed application and execution platform are developed. In this way, AADS-T
enables the verification of the initial timing constraints during the complete design process. In this paper we focus on the compatibility of AADS-T with the Ravenscar Computational Model (RCM) as part of the TASTE toolset. Its flexibility enables AADS-T to support different processors. In this work we have focused on
performing the simulation of the application running on a LEON2 processor.
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