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|A Framework for the Generation from UML/MARTE Models of IP/XACT HW Platform Descriptions for Multi-Level Performance Estimation
|Proceedings of the Forum of Design and Specification Languages 2011 (FDL'2011)
Design and verification of HW/SW embedded systems
FP7 IP 247999 COMPLEX
|This paper presents a framework which automates the generation of the IP/XACT-based description of the HW platform of an embedded system from a UML/MARTE model of such a system. The generator is integrated in a design exploration framework where the whole system is specified in UML, taking MARTE as reference profile, and which requires the generation of the platform information in an intermediate format, to feed the toolset in charge of the generation of executable models for performance estimation at different abstraction levels. The presented framework enables the generation of HW platform descriptions based on the IP/XACT standard, where the level of information is suited to the needs of the abstraction levels handled by the TLM executable models generated (namely, native-source and ISS-based performance estimation). The generator has been fully integrated in Eclipse as part of the design exploration framework, and as a standalone plug in.