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| GIM>Research>Publication |
| PUBLICATION |
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| Full record |
| Title: | Modeling and SW Synthesis for Heterogeneous Embedded Systems in UML/MARTE |
| Type: | International Conference |
| Where: | Tutorial SD1: "High-Level Specifications to Cope With Design Complexity" in ASP-DAC 2014, Singapore
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| Date: | 2014-01 |
| Authors: |
Eugenio Villar
Alejandro Nicolás
Pablo Peñil
Héctor Posadas
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| R&D Lines: |
Design and verification of HW/SW embedded systems
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| Projects: |
FP7 288307 PHARAON
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| ISBN: | |
| PDF File: | see file
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| Abstract: | Design abstractions are key to deal with design complexity of high-performance computer system, mobile embedded system, and real-time automobile system. In Electronic System Level (ESL) design we have enjoyed abstractions above the Register Transfer Level (RTL) up to Transaction Level Modeling (TLM). Much research work starts with a behavioral specification of the system functionality captured in a System-Level Description Language (SLDL) and then focuses on identifying heterogeneous allocation, mapping and scheduling. Crucial aspects already locked down include algorithm quality, parallelization potential (task-, data-, and instruction-level parallelism), demands on local data storage, and amount of traffic. Therefore a sufficiently flexible, parallelism exposing specification is paramount to enable meaningful design space evaluation.
The tutorial highlights opportunities and methods to describe, simulate and automatically generate the SW stacks on heterogeneous platforms using UML/MARTE.
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