Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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   PUBLICATIONS originated within the project: "ESPRIT 8370 ESIP..." ordered by date
 
   1996
International Conference E. Villar
"VHDL in Spain"
VHDL International User´s Forum. Santa Clara, CA, USA. 1996-03
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   1995
Report, Study or Opinion by order E. Villar
"Level-0 VHDL synthesis syntax and semantics"
CENELEC TC117 ENV. 1995-12
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Report, Study or Opinion by order E. Villar
"Part of Standardization activities: The synthesis package", Part 1, Vol.I"
Deliverable 204 of the ESPRIT 8370 ESIP project. 1995-10
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Report, Study or Opinion by order L. Entrena, S. Olcoz, P. Sánchez, E.Villar, J. Uceda, T. Riesgo
"Final report on the achievements of the ESIP fault modeling and simulation activity"
Deliverable 216 of the ESPRIT 8370 ESIP project. 1995-09
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International Conference E. Villar, P. Sánchez
"CAD tools for synthesis"
proc. of the IEEE International Synposium on Industrial Electronics, ISIE'95, Athens, Greece. 1995-07
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Report, Study or Opinion by order L. Entrena, L. Berrojo, S. Olcoz, P. Sánchez, E. Villar, J. Uceda, T. Riesgo
"Report on logic and RTL fault modeling"
Deliverable 214 of the ESPRIT 8370 ESIP project. 1995-03
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Complete book E. Villar, M. Altmäe
"Language requirements for high-level synthesis"
CENELEC TC117 report. 1995-01
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   1994
Report, Study or Opinion by order E. Villar, A. Debreil
"Synthesis and formal proof language support"
CENELEC TC117 report. 1994-09
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Report, Study or Opinion by order E. Villar, L. Berrojo, A. Debreil, B. Fjellborj, M. Mentes, C-W. Lee, N. Jansson
"Standardization activities: The synthesis package"
Deliverable 203 of the ESPRIT 8370 ESIP project. 1994-07
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