Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
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Título:Assertion Checking of Behavioral Descriptions with Non-linear Solver
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:IEEE International Conference on Computer Design
Fecha:2005-10
Autores: Iñigo Ugarte
Pablo Pedro Sánchez
Líneas:
Proyectos:
ISBN:0-7695-2451-6
Fichero:
Resumen:Verification has become the mayor bottleneck of the
design process. According to the latest report of the
International Technology Roadmap for
Semiconductors, the challenge will be to develop new
design-for-verifiability techniques and verification
methods for higher levels of abstraction. Several
Design-for-Verifiability methodologies (DFV) have
been proposed and Assertion-based Verification (ABV)
is one of the most promising. In order to automatically
verify assertions at the higher abstraction levels, it is
necessary to improve the performances and
capabilities of current constraint solvers.
This paper presents a new technique based on nonlinear
solvers that automatically checks assertions in
behavioral descriptions of hardware systems. These
descriptions are modeled with a set of integer
polynomial inequalities. The technique provides better
results than SAT solvers and it is applied to real
designs, such as Viterbi decoders or vocoder digital
filters.
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