| Ficha completa |
| Título: | Formal Meaning of Coverage Metrics in Simulation-based Hardware Design Verification |
| Tipo: | Publicacion en Proceedings o Actas internacionales |
| Lugar: | IEEE International High-Level Design Validation and Test Workshop
California |
| Fecha: | 2005-11 |
| Autores: |
Iñigo Ugarte
Pablo Pedro Sánchez
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| Líneas: |
Diseño y verificación de sistemas embebidos HW/SW
|
| Proyectos: |
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| ISBN: | 0-7803-9571-9 |
| Fichero: |
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| Resumen: | As the latest version of the International Technology
Roadmap for Semiconductors highlights, verification has
become the dominant cost of the electronic system design
process. Although advances in formal methods have improved
some aspects of the task, software simulation remains the
primary method of functional verification.
Traditionally, heuristic coverage metrics have been used to
evaluate the simulation-based validation process and the
development of coverage-driven random-based test bench
generation techniques is allowing the automation of the
functional verification process.
This coverage-based approach has a very serious
disadvantage: the metrics have no formal meaning and so
there is no direct correlation between classes of bugs and
coverage metrics.
The main goal of this paper is to explore methods that provide
a formal meaning to coverage metrics with random test
benches. They are independent of a particular fault or bug
model. The methods are based on polynomial models of the
system under verification and they can evaluate data and
control statements. |
