Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
Home   Personas   Investigación   Docencia   Doctorado   Publicaciones   Herramientas   Bolsa de Empleo   english version Sat 22-Jun-24 . 14:21

Mapa Web



Info Santander

Gestión BD

   Ficha completa
Título:Functional Vector Generation for Assertion-Based Verification at Behavioral Level Using Interval Analysis
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:IEEE International High Level Design Validation and Test Workshop HLDVT’03, San Francisco, CA
Autores: Iñigo Ugarte
Pablo Pedro Sánchez
Líneas: Diseño y verificación de sistemas embebidos HW/SW
Resumen:The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts that it is unlikely that verification will be manageable for designs envisioned beyond 2007 without Design-for-Verifiability. Some CAD vendors have promoted Assertion-Based Verification (ABV) as one of the first commercial Design-for-Verification techniques. In order to handle complex design, this methodology has to be complemented with tools that automatically generate vectors or counterexamples that violate/verify proposed assertions or constraints. This paper presents an assertion checking technique for behavioral models that combines a non-linear solver and state exploration techniques and avoids expanding behavior into logic equations. The kernel of the technique is a MODified Interval Analysis (MODIA) that avoids most of the problems of classical interval analysis (IA) and improves reuse during vector generation. The results show that the proposed technique is able to handle very efficiently data-dominated designs, which research and commercial assertion/property checkers are unable or need more CPU effort to verify.
© Copyright GIM (TEISA-UC)    ¤    Todos los derechos Reservados.    ¤    Términos LegalesE-Mail Webmaster