Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
Home   Personas   Investigación   Docencia   Doctorado   Publicaciones   Herramientas   Bolsa de Empleo   english version Sat 22-Jun-24 . 14:17

Mapa Web



Info Santander

Gestión BD

   Ficha completa
Título:Analysis of Random Testbench for Data-Dominated Hardware Descriptions
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:XII IEEE European Test Symposium
Autores: Iñigo Ugarte
Pablo Pedro Sánchez
Resumen:As the latest version of the International Technology Roadmap for Semiconductors highlights, verification has become the dominant cost of the electronic system design process. Although advances in formal methods have improved some aspects of the task, software simulation remains the primary method of functional verification. Traditionally, heuristic coverage metrics have been used to evaluate the simulation-based validation process and the development of coverage-driven random-based test bench generation techniques is allowing the automation of the functional verification process. This coverage-based approach has a very serious disadvantage: the metrics have no formal meaning and so there is no direct correlation between classes of bugs and coverage metrics. The main goal of this paper is to explore methods that provide a formal meaning to coverage metrics with random test benches. They are independent of a particular fault or bug model. The methods are based on polynomial models of the system under verification.
© Copyright GIM (TEISA-UC)    ¤    Todos los derechos Reservados.    ¤    Términos LegalesE-Mail Webmaster