Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
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Título:Providing a Formal Meaning to Coverage Metrics
Tipo:Publicacion en Proceedings o Actas internacionales
Lugar:XXII Conference on Design of Circuits and Integrated Systems
Fecha:2007-11
Autores: Iñigo Ugarte
Pablo Pedro Sánchez
Líneas:
Proyectos:
ISBN:978-84690-8629-2
Fichero:
Resumen:Verification has become the dominant cost of the electronic system design process. Although advances in formal methods have improved some aspects of the task, simulation-based techniques are the main tools for verifying complex hardware designs. Simulation requires coverage metrics in order to minimize the number of simulations and provide a measure of quality of the set of test benches. This measure enables an acceptable level of verification to be established to consider the validation sufficient.
In this paper, different structural coverage metrics are analyzed at behavioral level (path coverage, statement coverage and branch coverage), providing a formal meaning to coverage metrics with random test benches. They are independent of a particular fault or bug model. A set of polynomial inequalities is used to model the design.
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