Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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GIM>Research>Lines
   RESEARCH LINES in which "Eugenio Villar" participates
 
Research Line
Design and verification of HW/SW embedded systems
Synthesis application of VHDL
Behavioral Synthesis
Design of HW/SW Embedded Systems
Activity in the Artemis Technology Platform
Previous activities in HW/SW Embedded Systems Design
Embedded Systems Specification
Previous activities in VHDL design
Design and verification of electronic systems for communications
Formation of engineers in design and test techniques for VLSI circuits
Verification of Embedded Systems

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