Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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GIM>Research>Previous activities ...
 Previous activities in HW/SW Embedded Systems Design
   Select these links to see PROJECTS or PUBLICATIONS within this research line
Eugenio Villar (Responsible for this Research Line)
Pablo Pedro Sánchez
Héctor Posadas
Jesús Angel Adámez
Juan Castillo
Margarita Díez
David Quijano
Once behavioral synthesis matured during the 90's to the level of the availability of commercial synthesis tools, the international research interest changed to new areas not efficiently solved yet. The growing complexity of integrated circuits, ASICs and FPGAs that currently may include several embedded microprocessors and/or DSPs in addition to the application-specific HW, requires the definition and development of new design methodologies for such complex HW/SW systems. In this field, the group oriented its research interest to the development of industrial design methodologies for complex HW/SW embedded systems. The first approach was the integration of the behavioral synthesis tool FIRES in co-design frameworks [Ta95][TaVi95a][TaVi95b][TaVi95c][TVVV96].

The participation to the Human Capital and Mobility Network BELSIGN [PRO95] ensured the development of these research activities in an international atmosphere of cooperation and interchange of knowledge and information.

Afterwards, the group participated in the ESPRIT 26971 CoMES [PRO98] project with Matra Bae Dynamics, INDRA-ESPACIO, SIDSA and IRESTE in the definition of a specification and functional design methodology for embedded systems [Vi99][RoVi99a][RoVi99b][RoVi99c][FCLO99].

The research activity continued with the FEDER project entitled "development of industrial design methodologies for HW/SW embedded systems" [PRO99]. In this project, a co-design methodology was proposed adapted to the small and medium-size enterprises which characterize the industrial structure in our country. With this aim, the methodology used public-domain languages, like SystemC and VHDL and minimized the need for tools with high acquisition and maintenance costs [RoVi00][HRFS00][FeVH01]. System specification is a key aspect of the methodology and was exercised on an industrial case study [HFRS00][FVH01][FHV01][VLB02]. From the SystemC specification, a systematic SW generation methodology including the scheduling of the different tasks on the selected RTOS, was developed [HSV02c][HPSV03a][HSV03b][HPSV03b][FHSV02]. This technology led to the SW synthesis library, SWGen. Main results of the project were presented in the Summer Course of the University of Cantabria in July 2001 [Sa01]. Several outstanding researchers in the field collaborated in the course [Vi01a].

The group participated as subcontractor to DS2 in the project Medea+ A511 ToolIP in the reusability of microprocessor cores [HSV02a][VSBR03]. As demonstrator, a reusable, OpenRisc 1500 architecture was designed in SystemC and implemented on a FPGA [BCSP02][BCHP03a][BCHP03b][BCPS03][BCPS04]. A reusable microprocessor requires the corresponding software development kit (SDK) and a modeling SystemC library (PERFIDY) able to provide the designer with an accurate estimation of the performance characteristics of a certain application running on a particular instantiation of the microprocessor platform [HPV02][Vi02b][BVH02][HSV02b][PHSV02][PHSV04].

The SystemC libraries for performance analysis and SW generation constitute a single-source approach for embedded system design. That is, the use of the same code for system-level specification and profiling, and, after architectural mapping, for HW/SW co-simulation and embedded software generation [PHFSV05].

The performance analysis technology developed in ToolIP was applied to the modeling and simulation of the execution support for real-time analysis of reusable COTS. This research activity was carried out in the ITEA IP 03002 MERCED project as subcontractor to DS2. A first result was the SystemC modeling and simulation of task scheduling in an RTOS [PAV04]. This work was the basis for the SystemC library for POSIX modeling and simulation (PERFidiX). By using the library, the application code is can be automatically simulated estimating the execution time of the application SW using POSIX functions running on the target HW platform [PVB05][PAV05][PAVSB06][PAVA06]. This work led to a general study of the application of SystemC to RTOS modeling. The POSIX implementation of PERFidiX served as an experimental case study [PAVEM05].

The RTOS modeling and simulation technology developed in MERCED was applied to the modeling of the HW-dependent SW (HdS) in multiprocessing, systems on chip (MpSoC) with network on chip (NoC) in the MEDEA+ 2A708 LoMoSa+ project as a subcontractor of DS2. In the project, the SW synthesis techniques from SystemC developed in [PRO99] were improved with the generation of HdS in MpSoC with NoC. The first activity was the specification of the HdS modeling methodology to be developed afterwards [QPSVM06]. A first result was the improvement of the RTOS model with the inclusion of HW interrupts and a TLM model of the bus [PQVEM06]. The library supports an abstract model of the communication drivers with peripherals as well as the associated DMA operations. All this over the TLM2 model of the bus [PQVM07]. The processing node can be part of a complete NoC. In this sense, the SystemC library has been extended with the network simulator Sicosys (SImulator for COmunication SYStems). The library has been integrated with the ORB CORBA model of TIMA. This allows abstraction of the NoC structure. The technique used for SW execution time estimation can be extended to the estimation of power consumption [CPVM07]. All these improvements represent an evolution of PERFidiX towards the new modeling and simulation tool for MpSoC with NoC, SCoPE [CPQSV06][VPM07][PQEM07]. This work allowed a global analysis of the actual capabilities of SystemC for behavioral simulation and performance estimation in heterogeneous, HW/SW embedded systems [PCQFV09]. Although most of the effort during the project was put on the development of SCoPE, preeliminary, promising results in the automatic generation of HdS from SystemC were obtained [DVM08].

During 2009, the Group participated to the Medea 2A714 SoftSoC project. During this time, the group contributed to the definition of the HdS architecture [FVV08] and the HdS modeling, simulation and performance analysis methodology [PeVi08].

In the project ITEA 05015 SPICES, methodologies for SystemC modeling of AADL specifications were developed. A first result was the especification of the modeling methodology [HeVi07a][HeVi07b][ViHe07]. Based on this specification, the SystemC simulation tool of AADL specifications, AADS[VaVi07], was developed [VaVi08][AADS09][VaVi09a][VaVi09b], improved afterwards with the 'Behavioral Annex' [VaVi10]. In this project, the Computers and Real-Time Group proposed techniques for Real-Time analysis and schedulability.
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