Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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GIM>Research>Activity in the Arte...
RESEARCH LINE:
 Activity in the Artemis Technology Platform
   Select these links to see PROJECTS or PUBLICATIONS within this research line
 
STAFF:
Eugenio Villar (Responsible for this Research Line)
Pablo Pedro Sánchez
Patricia Botella
Luis Diaz
Raúl Diego
Margarita Díez
Pablo González
Sara Real
WORK FIELDS:
The Group has participated in the European Embedded Systems Technology Platform ARTEMIS, since its creation in 2005. Since 2006, Eugenio Villar is the representative of the University of Cantabria in the industrial association of the ARTEMIS Platform, ARTEMISIA. The Group was member of PROMETEO the spanish Platform in relation to ARTEMIS. The technical activity in PROMETEO was carried out in the Singular Project ATENEA from 2006 to 2008.

The Group participated to the Scalopes project approved in the first call. The project addressed the paradigmatic shift of embedded computing platforms from simple, centralized (CPU + memory hierarchy + peripherals) architectures to heterogeneous multi-cores is propelled by ever-growing computational demands of applications and by the continuously tightening energy budgets dictated by technology and cost constraints. Scalope top-level goal is to enable an industrially sustainable path for the evolution of low-power multi-core computing platforms for application domains with strategic value for European competitiveness. The participation of the University of Cantabria (UC) allowed significant improvements in the modeling, simulation and performance analysis capabilities of the SCoPE tool. The effectiveness of these new features were shown in power consumption reductions and performance improvements in the video processing and transmission industrial demonstrators developed in cooperation with the two Spanish companies participating to the project VistaSilicon and TTI. More concretely, a novel data cache model for native simulation was developed which represent a significant improvement in the application of native simulation in memory modeling and performance analysis [DPV10][PDV11a]. This technique and its application to L2 modeling and estimation of memory simulation and power consumption has been patented [PDV11b]. A tool was developed able to automatically create the SCoPE model of a symmetric, multi-processing (SMP) node as a SystemC component to be integrated in the complete system model. The input information is the number and type of the processors and the internal memory architecture [BSP10][CBD10]. In order to improve system composability, a tool for automatic composition of the SCoPE simulation model from the IP-XACT model of the architecture of processors, memories, SMP nodes, peripherals, co-processors, application-specific HW, etc., was developed. The UC gave support to TTI in the use of this technology in the component packaging of a system for mobile antennas positioning, tracking and data acquisition (PAC) [CVM10a][CVM10b]. The main technical contributions were the improvements in SCoPE in modeling and performance analysis, mainly power consumption in heterogeneous, multi-processing systems, able to face the challenges of power optimization without performance degradation and improvements in design productivity targeted by the Scalopes project [GSD10][VCA10a]. An interesting contribution showing the advantages provided by native simulation in architectural optimization is the efficient modeling and simulation of dynamic voltage-frequency scaling (DVFS). This technique is increasingly used in multi-processing systems in order to optimize the ratio power consumption versus performance. The collaboration with Politecnico di Torino and ST enabled the integration of SCoPE with PoTest, the thermal analysis tool. The combination of both tools allows thermal analysis of the integrated system during architectural design and floorplanning avoiding late detection of potential thermal problems after layout generation with a significant saving of time and effort in the design process [CaVi10][VCA10b][DGH11][CGD11]. Other important improvements relate to the backannotation technique from the binary with a better handling of compiler optimizations, a wider coverage of the POSIX API, the execution time and power consumption estimation of the system calls, the integration in the tool of the DVFS modeling and the development of a Win32 API for native simulation [BVD11]. Finally, solutions for seamless integration of the different systems components into a global system model with automatic generation of the "Hardware-dependent Software" from the IP-XACT components and integration of SW communication components like the TCP/IP stack, were develped [PoVi10][CPV10][CBP11]. All the technical contributions were validated in the industrial demonstrator of smart video processing where it was shown that the use of the improved SCoPE allowed a reduction of power consumption around 61% while increasing performance in 54.8%. The improvement in simulation and performance analysis reduced design time by 40% [BGS10][CGD11][PeSa10] with respect to the main alternatives (ISS and virtualización) [Vi10].

The COPCAMS project aimed at the application of the new multi-processing platforms in the realization of a new generation of intelligent cameras capable of extracting the relevant information from the captured images and reacting autonomously to the changes in the conditions detected in the environment. It is about facilitating the design and deployment of cognitive and perceptual camera systems. The University of Cantabria contributed to the development of new 3D video algorithms and their efficient implementation in heterogeneous multi-processor platforms. One of the main research activities was the development of VIPPE [DGV14][DGV15], a parallel version of SCoPE. However, the main result was the generation of a patent that allows to position objects in a 3D space with applications in Mixed Reality and the development of the corresponding proof of concept [VMA14][ViMa16].
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