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|Generation of Abstract IP/XACT Platform Descriptions from UML/MARTE for System-Level Performance Estimation
|W6: 2nd Workshop on Model Based Engineering for Embedded Systems Design, DATE 2011
Design and verification of HW/SW embedded systems
FP7 IP 247999 COMPLEX
|UML/MARTE is enabling the development of methodologies for the specification of a whole real-time system, and of holistic MDA methodologies where the UML/MARTE description is taken as the source for different design activities, such as system-level performance estimation and implementation refinement. A crucial issue to make these methodologies working and efficient is the development of
tools, such as code generators, able to handle and produce from the UML/MARTE model the level of information required by each specific design activity. In this line, this paper proposes a framework for the automatic generation of abstract IP/XACT descriptions of the HW platform of a system, synthetic and suitable for system-level performance estimation. Moreover, this paper shows the suitability of this framework for multi-level generation, which, in this case, means a scalable generation of the information in the IP/XACT description to
satisfy the needs of different design levels, ranging from system-level performance estimation to implementation.