Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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   PUBLICATIONS pertaining to the research line: "Design and verification of electro..." ordered by date
 
   2010
Report, Study or Opinion by order Artur Wegele, P. Peñil, E. Villar, Wolfgang Mueller, Da He, Fabian Mischkalla, et. al.
"Updated frameworks"
Deliverable D4.5 the FP7-216807 SATURN Project. 2010-12
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International Conference J. Pérez, V. Fernández
"3GPP2/802.20 RC/QC-LDPC Encoding"
IEEE European Wireless 2010, Lucca, Italy. 2010-04
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   2009
National Patent J. Pérez, V. Fernández
"Codificador ldpc e interleaver para dvb-s2"
Oficina Española de Patentes y Marcas. OEPM . 2009-09
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   2008
International Conference J. Pérez, V. Fernández
"Reducing the error floor using a two-level permutation in structured eIRA LDPCs"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2008), Grenoble, France. 2008-11
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International Paper J. Pérez, V. Fernández
"Low-Cost Enconding of IEEE 802.11n"
IET Electronics Letters Volume 44, Issue 4, pp. 307-308. 14 Feb 2008. 2008-03
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   2007
International Paper J. Pérez, K. Andrews
"Low-Density Parity-Check Code Design Techniques to Simplify Encoding"
The Interplanetary Network Progress Report, Volume 42-171, Jet Propulsion Laboratory (NASA), California Institute of Technology, Pasadena, California. 2007-11
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   2006
International Conference J. Pérez, V. Fernández
"Improved Architectures for VLC MAP decoders"
IEEE International Symposium on Wireless Communication Systems (ISWCS), Valencia, Spain. 2006-09
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International Conference J. Pérez, V. Fernández, Fernando Vallejo, Ana Jalón
"Novel DVB-S2 FEC Encoder Architecture"
9th International Workshop on Signal Processing for Space Communications. ESTEC, Noordwijk, The Netherlands. 2006-09
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International Conference J. Pérez, V. Fernández
"Hierarchical and Pseudo-Random eIRA Codes Based on BIBDs and Primitive Interleavers"
IEEE International Conference on Wireless Information Networks and Systems, Setubal, Portugal. 2006-08
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International Conference J. Pérez, V. Fernández
"Near Random Performance of Structured eIRA Codes"
IEEE and IEE co-sponsored Signal Processing for Wireless Communications (SPWC) Workshop, London. 2006-05
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   2005
International Conference J. Pérez, V. Fernández
"Hardware Aware eIRA LDPC Code Generation"
IEEE International Symposium of Wireless Communication Systems 2005(ISWCS 2005), Siena, Italy. 2005-09
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International Conference J. Pérez, V. Fernández
"Optimizations in max-log-map LLRe VLSI architecture"
IEEE International Symposium on Signals, Circuits and Systems (ISSCS). Iasi (Romania) . 2005-07
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   2004
International Conference J. Pérez, V. Fernández
"Optimizations in DVB-RCS Turbo Decoder Based on Trellis Structure"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2004). Bordeaux. 2004-09
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Report, Study or Opinion by order J. Pérez, V. Fernández, H. Posadas, V. Fernández
"Estudio de viabilidad de DVB-S2 en Banda Ka"
Memoria técnica justificativa del proyecto PROFIT PNE-001/2003-EMP. 2004-04
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   2003
International Conference J. Pérez, P. Sánchez, V. Fernández
"FGPA Implementation of a MAP Decoder for DVB-S Satellite Reception"
XVIII Conference on Design of Circuits and Integrated Systems (DCIS2003). Ciudad Real. 2003-11
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   2002
International Conference V. Fernández, A. Jalón, L. Berrojo, Yves Leroy
"Design, Functional Verification and Test of a MPEG2-TS Multiplexer for an On-Board Satellite Processor"
XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002). Santander. 2002-11
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International Conference J. Pérez, P. Sánchez
"FPGA implementation of DVB-RCS turbo coder and decoder"
Proceedings of the XVII Design of Circuits and Integrated Systems Conference, Servicio de Publicaciones de la Universidad de Cantabria. 2002-11
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   2001
International Conference V. Fernández, L. Berrojo, J. Prat, Y. Leroy
"Verification of a Digital Video Broadcasting Satellite System"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11
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   2000
International Conference L. Chen, S. Dey, P. Sánchez, K. Sekar, Y.H. Chen
"Embedded Hardware and Software Self-Testing Methodologies for Processor Cores"
37th Design Automation Conference, Los Angeles, California. 2000-06
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   1998
International Conference A. Antón, E. Villar, D.B. de Vries & S.M. H. de Groot
"Design and functional description of a sender and receiver for ATM adaptation layer protocols"
XIII Design of Circuits and Integrated Systems Conference (DCIS98). Madrid. 1998-11
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Complete book Ll. Terés, Y. Torroja, S. Olcoz, E. Villar
"VHDL: Lenguaje estándar de Diseño Electrónico"
McGraw Hill. 1998-01
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Book chapter E. Villar, P. Sánchez
"Síntesis"
VHDL: Lenguaje estándar de diseño electrónico McGraw-Hill. 1998-01
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International Paper A. Antón, E. Villar, D.B. de Vries, S. M. H. de Groot.
"Flexible architecture for processing ATM adaptation layer protocols (AAL1-5)"
IEEE Journal of Electrical Engineering, V.49, N.3-4, pp. 70-75. 1998-01
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International Paper P. Tabuenca, E. Villar
"An algorithm for clock cycle selection in behavioral synthesis"
Journal of Systems Architecture, V.44, N.9-10, North-Holland, pp. 773-786. 1998-01
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   1997
International Conference A. Antón, E. Villar, D. B. de Vries, S.M. Heemstra de Groot
"Design and functional description of a receiver for ATM Adaptation Layer Protocols"
6th HCM BELDESIGN Workshop. Aveiro (Portugal). 1997-10
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International Conference A. Antón, E. Villar, S.M. Heemstra de Groot, D. B. de Vries
"Flexible Architecture for Processing ATM Adaptation Layer Protocols (AAL1-5)"
First Electronic Circuits and Systems Conference (ECS97). Bratislava (Slovakia). 1997-09
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   1996
International Conference J. L. Barreda, P. Sánchez
"Current fault modeling in VITAL"
XI Conference Design of Integrated Circuits and Systems (DCIS´96). Sitges (Barcelona).. 1996-11
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International Conference H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"Design of a Flexible Architecture for Processing ATM Adaptation Layer Protocols"
ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. Mierlo (The Netherlands). 1996-11
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International Conference H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"A Flexible Architecture for Processing ATM Adaptation Layer Protocols"
4th HCM BELSIGN Workshop, Santander. 1996-10
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International Conference J. L. Barreda, P. Sánchez
"Current modeling in VITAL"
ATW Workshop. 1996-06
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International Paper M. Imai, E. Villar
"ASPDAC 1995: HDL synthesizability and interoperability"
IEEE Design & Test of Computers. Panel Summaries, pp 3-4. 1996-04
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International Paper W. Ecker, E. Villar
"VHDL multi-wait descriptions for synthesis"
Working Conference of VHDL Forum for CAD in Europe, Dresden Germany, pp 59-69. 1996-04
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International Paper H.W.A. Teunissen, D.B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"Design of a flexible architecture for processing ATM adaptation layer protocols"
CTIT Technical Report series, N. 96-40 University of Twente, The Netherlands. 1996-01
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International Paper M. Selz, W. Ecker, E. Villar
"VHDL synthesis description portability: The need for Level-x synthesis subsets"
Journal of System Architecture 42, North-Holland, pp 105-116. 1996-01
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   1995
International Paper E. Villar
"The Level-0 VHDL Synthesis Syntax and Semantics - 2nd Part"
The VHDL Newsletter, No. 20, pp.1 and 12. 1995-12
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National Conference COMITE PRENDA
"Importancia de una metodología para las nuevas técnicas de diseño de ASICs"
X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11
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International Paper E. Villar
"The Level-0 VHDL Synthesis Syntax and Semantics - 1st Part"
The VHDL Newsletter, No. 19, pp. 10-11. 1995-10
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International Conference J. L. Barreda, I. Hidalgo, V. Fernández, P. Sánchez, E. Villar
"Fault Modeling in VITAL"
Proceedings of the Workshop on Libraries, Component Modeling, and Quality Assurance. Nantes, France. 1995-04
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International Conference M. Selz, W. Ecker, E. Villar
"VHDL synthesis description portability: The need for Level-x Synthesis Subsets"
Spring´95 Working Conference of the VHDL Forum for CAD in Europe. Nantes (France). 1995-04
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Report, Study or Opinion by order Pedro Tabuenca, E. Villar, L. Muñoz, R. Sanz
"Estudio de viabilidad de la implementación ASIC"
Documento Final del proyecto GAME "Análisis de viabilidad de un ASIC para chasis de baja". 1995-03
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Complete book Comité PRENDA
"Metodología para el diseño de ASICs"
Documento Entregable PRENDA/ENT/T14-01/CON del proyecto GAME PRENDA. 1995-02
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National Paper C. Delgado Kloos, E. Villar
"VHDL: El lenguaje estándar de diseño electrónico"
Novática. 1995-01
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   1994
Complete book Comité PRENDA
"Guia de referencia general de la metodología"
Documento entregable del proyecto GAME PRENDA. 1994-10
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National Conference Comité PRENDA
"Proyecto para la especificación y normalización en el diseño de ASICs (PRENDA)"
III Jornadas Técnicas de Calidad en Tecnologías Electrónicas, T.I+D, Madrid. 1994-10
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