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| GIM>Research>Publications |
| PUBLICATIONS in which "Luis Diaz" participates ordered by date |
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| 2017 |
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H. Posadas, L. Diaz, E. Villar
"Static Write Buffer Cache Modeling to Increase Host-compiled Simulation Accuracy "
Euromicro Conference on Digital System Design (DSD). 2017-09 |
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| 2015 |
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L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE: Parallel simulation and performance analysis of complex embedded systems"
HiPPES4CogApp: High Performance, Predictable Embedded Systems for Cognitive Application. 2015-01 |
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| 2014 |
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L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE, parallel simulation and performance analysis of multi-core embedded systems on multi-core platforms"
XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014. 2014-11 |
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P. González, Á. Díaz, L. Diaz, P. Sánchez
"Profiling and optimizations for Embedded Systems"
ACM-IEEE MEMOCODE14. 2014-10 |
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L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE: Native simulation and performance analysis framework for multi-processing embedded systems"
Proceedings of the JCE-Sarteco 2014. 2014-09 |
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L. Diaz, P. Sánchez
"Host-compiled Parallel Simulation of Many-core Embedded Systems"
San Francisco, DAC2014. 2014-06 |
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P. Peñil, L. Diaz, P. Sánchez
"Sytem-level design framework for many-core architectures
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Workshop 3PMCES 2014. 2014-03 |
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| 2011 |
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D. Calvo, P. González, L. Diaz, Alvaro Diaz, Pablo Sanchez, D. Gutiérrez (TTI), F. Alcalá (VS)
"Smart video processing in MPSoC demonstrator"
Deliverable DA2.3b of Artemis SCALOPES Project. 2011-03 |
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D. Calvo, P. González, L. Diaz, H. Posadas, P. Sánchez, E. Villar, Andrea Acquaviva, Enrico Macii
"A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design"
ASP Journal on Low-Power Electronics (JOLPE): Special Issue on Low Power Design and Verification Techniques
. 2011-02 |
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H. Posadas, L. Diaz, E. Villar
"Fast Data-Cache Modeling for Native Co-Simulation
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Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011-01 |
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| 2010 |
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L. Diaz, H. Posadas, E. Villar
"Obtaining Memory Address Traces from Native Co-Simulation for Data Cache Modeling in SystemC"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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P. González, P. Sánchez, L. Diaz
"Embedded software execution time estimation at different abstraction levels"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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D. Calvo, P. Botella, L. Diaz, Saeid Azmoodeh, Francisco Barat, E. Villar, Philippe Millet
"Final report on CPD System component and model implementation"
Deliverable DT2.3.2 of the Artemis Scalopes project. 2010-11 |
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H. Posadas, L. Diaz, E. Villar
"Método y sistema de modelado de memoria caché"
Oficina Española de Patentes y Marcas. OEPM. 2010-10 |
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