Grupo de Ingeniería Microelectrónica

Grupo de Ingeniería Microelectrónica

Departamento de Tecnología Electrónica, Ingeniería de Sistemas y Automática Universidad de Cantabria
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   PUBLICACIONES en las que participa: "Pablo Pedro Sánchez" ordenadas por línea de investigación
 
   Diseño de circuitos electrónicos de aplicación industrial
conferencia J. Pérez, P. Sánchez
"Real-Time Stereo Matching using memory-efficient Belief Propagation for High-definition 3D tele-presence systems"
Iberoamerican Congress on Pattern Recognition (CIARP-2009). Guadalajara, Mexico. 2009-11
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   Diseño y verificación de sistemas electrónicos para comunicaciones
conferencia J. Pérez, P. Sánchez, V. Fernández
"FGPA Implementation of a MAP Decoder for DVB-S Satellite Reception"
XVIII Conference on Design of Circuits and Integrated Systems (DCIS2003). Ciudad Real. 2003-11
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conferencia J. Pérez, P. Sánchez
"FPGA implementation of DVB-RCS turbo coder and decoder"
Proceedings of the XVII Design of Circuits and Integrated Systems Conference, Servicio de Publicaciones de la Universidad de Cantabria. 2002-11
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conferencia L. Chen, S. Dey, P. Sánchez, K. Sekar, Y.H. Chen
"Embedded Hardware and Software Self-Testing Methodologies for Processor Cores"
37th Design Automation Conference, Los Angeles, California. 2000-06
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libro_c E. Villar, P. Sánchez
"Síntesis"
VHDL: Lenguaje estándar de diseño electrónico McGraw-Hill. 1998-01
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conferencia J. L. Barreda, P. Sánchez
"Current fault modeling in VITAL"
XI Conference Design of Integrated Circuits and Systems (DCIS´96). Sitges (Barcelona).. 1996-11
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conferencia J. L. Barreda, P. Sánchez
"Current modeling in VITAL"
ATW Workshop. 1996-06
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conferencia J. L. Barreda, I. Hidalgo, V. Fernández, P. Sánchez, E. Villar
"Fault Modeling in VITAL"
Proceedings of the Workshop on Libraries, Component Modeling, and Quality Assurance. Nantes, France. 1995-04
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   Métodos de test de circuitos integrados digitales y mixtos
conferencia I. Hidalgo, P. Sánchez
"System Level Fault Simulation"
BELSIGN Workshop. Corcega. 1996-04
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conferencia J. L. Barreda, P. Sánchez, E. Villar
"Current fault modeling in VITAL"
VHDL International User´s Forum. Santa Clara, CA, USA. 1996-02
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conferencia_n I. Hidalgo, P. Sánchez
"Técnica para simulación de fallos en un entorno VHDL"
Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11
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conferencia_n V. Fernández, P. Sánchez
"Síntesis de alto nivel para scan parcial"
Actas del Congreso de Diseño de Circuitos Integrados y Sistemas. Zaragoza. 1995-11
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   Diseño y verificación de sistemas embebidos HW/SW
conferencia Á. Díaz, E. Villar, P. Sánchez
"Integrated Framework for Reusable Multi-Level Embedded System Verification"
Work-in-Progress Session, DAC, San Francisco. 2018-06
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patente_int E. Villar, P. Martínez, F. Alcalá, P. Sánchez, V. Fernández
"Método y sistema de localización espacial mediante marcadores luminosos para cualquier ambiente"
Oficina Española de Patentes y Marcas, OEPM. 2015-11
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conferencia A. Quevedo, G. Callico, S. López, R. Sarmiento, A. Nicolás, P. Sánchez, E. Villar
"System Level Methodology based on VIPPE applied to the implementation of a Scalable Video Decoder on the ZynQ platform"
Conference on Design of Circuits and Integrated Systems, DCIS 2015. doi: 10.1109/DCIS.2015.7388604. 2015-11
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conferencia P. Peñil, P. Sánchez, David de La Fuente, Jesús Barba, Juan Carlos López, Xerach Peña
"Building a Dynamically Reconfigurable System Through a High-Level Development Flow"
Forum on specification & Design Languages (FDL 2015). 2015-09
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conferencia L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE: Parallel simulation and performance analysis of complex embedded systems"
HiPPES4CogApp: High Performance, Predictable Embedded Systems for Cognitive Application. 2015-01
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conferencia_n Javier González Bayón, P. Sánchez, Javier Barreda
"Efficient Implementation of Pattern Matching Recognition in Heterogeneus Architectures"
XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014. 2014-11
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conferencia L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE, parallel simulation and performance analysis of multi-core embedded systems on multi-core platforms"
XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014. 2014-11
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conferencia L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE: Native simulation and performance analysis framework for multi-processing embedded systems"
Proceedings of the JCE-Sarteco 2014. 2014-09
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conferencia L. Diaz, P. Sánchez
"Host-compiled Parallel Simulation of Many-core Embedded Systems"
San Francisco, DAC2014. 2014-06
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conferencia P. Peñil, P. Sánchez, D. de la Fuente, J. Barba, J.C. López
"UML/MARTE methodology for automatic SystemC code generation of OPENMAX multimedia applications "
Euromicro Conference on Digital System Design, DSD 2013, IEEE. 2013-09
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conferencia Á. Díaz, J. González, P. Sánchez, P. González
"Virtual platform for power and security analysis of wireless sensor network"
SPIE 2013. 2013-04
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conferencia Á. Díaz, P. Sánchez, J. Sancho, J. Rico
"Wireless Sensor Network Simulation for Security and Performance Analysis"
DATE 2013. 2013-03
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revista P. González, J. González, P. Sánchez
"OpenMP performance analysis for many-core platforms with non-uniform memory access"
IJCSI Volume 10, Issue 2. 2013-03
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conferencia F. Herrera, H. Posadas, P. Peñil, E. Villar, P. Sánchez, P. González, F. Ferrero (GMV), R. Valencia (GMV)
"A MDD Methodology for the Specification and Performance Estimation of Embedded Systems"
Tutorial B: Advanced Techniques for Power-Aware System-Level Prototyping, DATE'13. 2013-03
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conferencia Á. Díaz, P. Sánchez, J. Sancho, J. Rico
"Simulation of attacks in Wireless Sensor Network"
DCIS 2012. 2012-11
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conferencia P. González, P. Sánchez, J. González
"A virtual Platform for performance estimation of OpenMP Programs"
DCIS 2012. 2012-11
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conferencia P. González, J. González, P. Sánchez
"An approach for algorithm parallelization oriented to a many-core implementation"
ISPA 2012. 2012-11
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conferencia Á. Díaz, P. Peñil, P. Sánchez, J. Sancho, J. Rico
"Modeling and Simulation of Secure Wireless Sensor networks"
Proceedings of the 2012 Forum on Specification and Design Languages, FDL'2012, IEEE. 2012-09
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conferencia Á. Díaz, R. Diego, P. Sánchez
"Virtual Platform for Wireless Sensor Network"
DSD Euromicro 2012. 2012-09
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conferencia P. González, P. Sánchez, J. González
"Hardware Performance Estimation by Dynamic Scheduling"
Proceedings FDL. 2011-12
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conferencia P. González, J. González, P. Sánchez
"Hardware Performance estimation by Dynamic Scheduling II"
Proceedings DCIS2011. 2011-12
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conferencia P. González, P. Sánchez
"An approach for modelling parallelization in the P2012"
P2012 Developers Conference. Grenoble.. 2011-12
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conferencia D. Calvo, J. Pérez, P. González, R. Diego, Á. Díaz, P. Sánchez
"Design, modeling and development of an efficient comunication infrastructure for networking applications"
XXVI Conference on Design of Circuits and Integrated Systems, DCIS'11. 2011-11
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conferencia D. Calvo, P. González, H. Posadas, P. Sánchez, E. Villar, Andrea Acquaviva, Enrico Macii, Claudio Parrella, Mateo Giaconia
"SCoPE: SystemC Cosimulation and Performance Estimation. Application to Power and Thermal-Aware Design"
University Booth, DATE 11, Grenoble. 2011-03
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conferencia D. Calvo, P. Botella, H. Posadas, P. Sánchez, E. Villar
"Automatic Generation of HdS System Model for System Simulation using IP-XACT"
Workshop W7: Hardware Dependent Software Solutions for SoC Design, DATE 2011. 2011-03
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revista D. Calvo, P. González, L. Diaz, H. Posadas, P. Sánchez, E. Villar, Andrea Acquaviva, Enrico Macii
"A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design"
ASP Journal on Low-Power Electronics (JOLPE): Special Issue on Low Power Design and Verification Techniques . 2011-02
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conferencia P. González, P. Sánchez, L. Diaz
"Embedded software execution time estimation at different abstraction levels"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11
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conferencia P. Botella, P. Sánchez, H. Posadas
"Automatic Generation of SystemC SMP Models for HW/SW Co-Simulation"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11
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conferencia J. Pérez, P. Sánchez
"Real-Time Voxel-Based Visual Hull Reconstruction"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11
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conferencia J. Pérez, V. Fernández, P. Sánchez
"Optimizing Data-Flow Graphs with Min/Max, Adding and Relational Operations"
Design Automation and Test in Europe 2010, DATE'10. 2010-03
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conferencia J. Barreda, P. Sánchez, Jorge Ocón
"Integration of Domain-Specific Models into a MDA Framework for Time-Critical Embedded Systems"
Sixth Workshop on Intelligent Solutions in Embedded Systems WISES 08. 2008-07
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informe J. Castillo, H. Posadas, D. Quijano, P. Sánchez, E. Villar
"HdS modeling library"
DS2-T3.4-Q2/07 Deliverable of the Medea+ 2A708 LoMoSa+ Project. 2007-06
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informe D. Quijano, H. Posadas, P. Sánchez, E. Villar, Marcos Martínez (DS2)
"Specification of HdS modeling methodology"
DS2-T3.4-Q2/06 Deliverable of the Medea+ 2A708 LoMoSa+ Project. 2006-06
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conferencia H. Posadas, J. Adámez, P. Sánchez, E. Villar, Francisco Blasco (DS2)
"POSIX modeling in SystemC"
proc. of the 11th Asia and South Pacific Design Automation Conference, ASP-DAC'06, IEEE. 2006-01
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conferencia I. Ugarte, P. Sánchez
"Formal Meaning of Coverage Metrics in Simulation-based Hardware Design Verification"
IEEE International High-Level Design Validation and Test Workshop California. 2005-11
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libro_c F. Herrera, P. Sánchez, E. Villar
"Heterogeneous system-level specification in SystemC"
"Advances in Design and Specification Languages for SoC", P. Boulet (Ed.), CHDL Series, Springer. 2005-10
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revista H. Posadas, F. Herrera, V. Fernández, P. Sánchez, E. Villar, F. Blasco
"Single Source Design Environment for Embedded Systems Based on SystemC"
Design Automation for Embedded Systems, V.9, N.4, Springer, pp.293-312. 2004-12
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conferencia F. Herrera, P. Sánchez, E. Villar
"Heterogeneous system-level specification in SystemC"
Proceedings of the Forum on Design Languages (FDL’04), Lille, ECSI. 2004-09
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libro_c F. Herrera, P. Sánchez, E. Villar
"Modeling and design of CSP, KPN and SR systems in SystemC"
"Languages for System Specification", C. Grimm (Ed.), CHDL Series, Kluwer Academic Publisher. 2004-06
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conferencia I. Ugarte, P. Sánchez
"Path-oriented Assertion Checking of Cyclic Behavioral Descriptions"
Formal Methods and Models for Co-Design MEMOCODE'04 California. 2004-06
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conferencia M. Bolado, H. Posadas, Javier Castillo, Pablo Huerta, P. Sánchez, Carlos Sánchez, Häkan Fouren, Francisco Blasco
"Platform based on open-source cores for industrial applications"
Proc. of DATE'04, IEEE CS Press. 2004-02
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conferencia H. Posadas, F. Herrera, P. Sánchez, E. Villar, F. Blasco
"System-Level Performance Analysis in SystemC"
proc. of DATE'04, IEEE CS Press. 2004-02
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informe M. Bolado, J. Castillo, P. Huerta, H. Posadas, P. Sánchez
"Implementation of a microprocessor core"
DS2-WP5-Q4/03 Deliverable of the Medea+ A511 TOOLIP Project. 2003-12
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conferencia E. Villar, P. Sánchez, F. Blasco, M. Radetzki, A. Vörg, Y. Wenhao
"Reusability of Microprocessor cores"
proc. of the MEDEA+ Design Automation Conference, Stuttgart. 2003-11
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conferencia I. Ugarte, P. Sánchez
"Functional Vector Generation for Assertion-Based Verification at Behavioral Level Using Interval Analysis"
IEEE International High Level Design Validation and Test Workshop HLDVT’03, San Francisco, CA. 2003-11
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informe M. Bolado, J. Castillo, P. Huerta, H. Posadas, P. Sánchez
"Executable specification of a microprocessor core"
UC-T2.1-Q3/03 Deliverable of the Medea+ A511 TOOLIP Project. 2003-09
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conferencia F. Herrera, P. Sánchez, E. Villar
"Modeling and design of CSP, KPN and SR systems in SystemC"
Proceedings of the Forum on Design Languages FDL'03, Frankfurt, ECSI. 2003-09
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conferencia I. Ugarte, P. Sánchez
"System Verification Based on Modified Interval Analysis"
European test Workshop, ETW’03. 2003-05
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conferencia F. Herrera, H. Posadas, P. Sánchez, E. Villar
"Systematic Embedded Software Generation from SystemC"
proc. of DATE'03, IEEE CS Press. 2003-02
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libro_c F. Herrera, V. Fernández, P. Sánchez, E. Villar
"Embedded Software Generation from SystemC for Platform Based Design"
"SystemC Methodologies and Applications", Kluwer Academic Publishers. 2003-01
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libro_c F. Herrera, H. Posadas, P. Sánchez, E. Villar
"Systematic Embedded software generation from SystemC"
"Embedded Software for SoC", Kluwer Academic Publishers. 2003-01
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informe M. Bolado, J. Castillo, C. Sánchez, H. Posadas, P. Sánchez
"Functional specification of a microprocessor core"
UC-T2.1-Q4/02 Deliverable of the Medea+ A511 TOOLIP Project. 2002-12
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informe H. Posadas, F. Herrera, P. Sánchez, E. Villar
"Library for microprocessor core analysis"
UC-T1.3-Q4/02 Deliverable of the Medea+ A511 TOOLIP Project. 2002-12
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conferencia F. Herrera, P. Sánchez, E. Villar
"HW/SW interface implementation from SystemC for platform-based design"
Forum on Design Languages FDL'02, ECSI. 2002-10
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conferencia E. Villar, P. Sánchez, H. Posadas
"System-level reusability of microprocessor cores in a SystemC specification environment"
MEDEA+ Design Automation Conference. 2002-09
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informe F. Herrera, P. Sánchez, E. Villar
"Comparative study for the selection of the processor core for SystemC specification"
UC/ToolIP/IR/01 Internal Report of the Medea+ A511 TOOLIP Project. 2002-06
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informe F. Herrera, P. Sánchez, E. Villar
"First draft of the library for microprocessor core analysis"
UC/ToolIP/IR/02 Internal Report of the Medea+ A511 TOOLIP Project. 2002-06
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informe I. Ugarte, P. Sánchez, E. Villar
"Metodología de Verificación y diseño para testabilidad digital"
Documento Entregable R3 del proyecto FEDER 1FD97-0791. 2002-03
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informe V. Fernández, F. Herrera, P. Sánchez, E. Villar
"Conclusiones: Metodología industrial de diseño de sistemas embebidos HW/SW"
Documento Entregable DF del proyecto FEDER 1FD97-0791. 2002-02
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libro_c P. Sánchez
"Embedded Software and RTOS"
"Design of HW/SW Embedded Systems", Edited by E. Villar, Servicio de Publicaciones de la Universidad de Cantabria. 2001-07
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informe F. Herrera, V. Fernández, R. Rodríguez, P. Sánchez, E. Villar
"Especificación del demostrador industrial"
Documento Entregable R2-C1 del proyecto FEDER 1FD97-0791. 2000-10
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revista S. Dey, D. Panigrahi, L. Chen, C. N. Taylor, K. Sekar, P. Sánchez
"Using a Soft Core in a SOC Design: Experiences with picoJava"
IEEE Design & Test of Computers. Pág. 60-71. 2000-07
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conferencia P. Sánchez, S. Dey
"Simulation-based system-level verification using polynomials"
IEEE International High Level Design Validation and Test Workshop HLDVT’99, San Diego, CA. 1999-11
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conferencia V. Fernández, P. Sánchez
"A Novel Approach To High-Level Test Synthesis Based On Controller Redefinition"
Proceedings of the European Test Workshop. Sitges, Spain. 1998-05
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libro_c V. Fernández, P. Sánchez
"Advanced Techniques for EMBEDDED SYSTEMS DESIGN & TEST, Capítulo 9, TEST SYNTHESIS OF DIGITAL SYSTEMS. "
Kluwer Academic Publishers. 1998-01
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conferencia A. López, M. Veiga, P. Sánchez, E. Villar
"ADA embedded system specification"
XII Design of Circuits and Integrated Systems Conference DCIS'97, Sevilla. 1997-11
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revista V. Fernández, P. Sánchez
"High-Level Test Synthesis based on controller redefinition"
IEE Electronics Letters, Vol. 33, No. 19, pp. 1596-1597. 1997-09
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conferencia V. Fernández, P. Sánchez
"Test Points Insertion For High-Level Test Synthesis"
Proceedings of the 4th Belsign Workshop. Santander, Spain. 1996-10
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conferencia V. Fernández, P. Sánchez
"Partial Scan High-Level Synthesis"
European Design & Test Conference. Paris, France. 1996-03
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conferencia V. Fernández, P. Sánchez, E. Villar
"A Novel High-Level Allocation Technique for Test"
Fourth Annual Atlantic Test Workshop. Corsica, France. 1995-07
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conferencia E. Villar, P. Sánchez
"CAD tools for synthesis"
proc. of the IEEE International Synposium on Industrial Electronics, ISIE'95, Athens, Greece. 1995-07
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conferencia V. Fernández, P. Sánchez, E. Villar
"Partial Scan High-Level Synthesis Strategy"
Second International Test Synthesis Workshop. Santa Barbara, CA (USA). 1995-05
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conferencia V. Fernández, P. Sánchez, Marta García, E. Villar
"Fault Modeling and Injection in VITAL Descriptions"
Proceedings of the Third Annual Atlantic Test Workshop, Nimes, France. 1994-06
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conferencia V. Fernández, P. Sánchez, E. Villar
"High Level Synthesis Guided by Testability Measures"
First International Test Synthesis Workshop, Santa Barbara, CA (USA). 1994-05
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conferencia E. Villar, P. Sánchez, V. Fernández
"High Level Synthesis with Testability Criteria"
2nd IEEE Annual Atlantic Test Workshop, Hanover, USA. 1993-06
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   Formación de ingenieros en técnicas de diseño y test de circuitos VLSI
conferencia_n P. Sánchez, E. Villar
"Docencia del VHDL: Experiencia en la E.T.S.I. Industriales y de Telecomunicación de la Universidad de Cantabria"
Jornadas de Tecnología Electrónica JTEC95. Las Palmas. 1995-02
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   Diseño de sistemas embebidos HW/SW
conferencia Á. Díaz, J. González, P. Sánchez, P. González
"Virtual platform for power and security analysis of wireless sensor network"
SPIE 2013. 2013-04
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conferencia Á. Díaz, P. Sánchez, J. Sancho, J. Rico
"Simulation of attacks in Wireless Sensor Network"
DCIS 2012. 2012-11
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conferencia Á. Díaz, R. Diego, P. Sánchez
"Virtual Platform for Wireless Sensor Network"
DSD Euromicro 2012. 2012-09
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informe Kai Hylla (OFFIS), Saif A. Butt (CV), F. Herrera, S. Real, P. González, P. Sánchez
"Preliminary report on Custom Hardware Estimation and Model Generation "
Deliverable D2.4.1 of the COMPLEX project. 2010-12
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   Verificación de sistemas embebidos
revista P. González, P. Sánchez
"Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification"
TCAD. 2017-03
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informe Kai Hylla (OFFIS), Saif A. Butt (CV), F. Herrera, S. Real, P. González, P. Sánchez
"Preliminary report on Custom Hardware Estimation and Model Generation "
Deliverable D2.4.1 of the COMPLEX project. 2010-12
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