Microelectronics Engineering Group

Microelectronics Engineering Group

Electronics Technology, Systems and Automation Engineering Department University of Cantabria
Home    Staff    Research    Teaching    Doctorate    Publications    Tools    versión en español Sat 20-Jul-24 . 06:25

Web Map



Santander Info

GIM>Research>Design of HW/SW Embe...
 Design of HW/SW Embedded Systems
   Select these links to see PROJECTS or PUBLICATIONS within this research line
Eugenio Villar (Responsible for this Research Line)
Víctor Fernández
Pablo Pedro Sánchez
Héctor Posadas
Patricia Botella
Daniel Calvo
Luis Diaz
Raúl Diego
Pablo González
Fernando Herrera
Alejandro Nicolás
Pablo Peñil
Sara Real
Roberto Varona
HW/SW Embedded Systems Design is one of the main activities currently carried out by the Research Group. In this field, the most active research area is modeling and performance analysis of HW/SW Embedded Systems. The performance analysis technology implemented in SCoPE was improved and applied to design space exploration in the FP7 216693 MULTICUBE. The project focused on the definition of an automatic multi-objective Design Space Exploration (DSE) framework to be used to tune the System-on-Chip architecture for the target application evaluating a set of metrics (e.g. energy, latency, throughput, bandwidth, QoS, etc.) for the next generation embedded multimedia platforms [SFP11]. The adaptation of SCoPE to the efficient performance analysis for DSE led to the development of the new tool MultiCube-SCoPE [PRV10]. Two kind of improvements were introduced. On the one hand, the adaptation of the simulation mechanism to the efficient performance analysis of a huge number of design space experiments [PMV09]. On the other, significant improvements in the modeling capabilities of SCoPE such us physical memory addresses [PoVi09], SystemC modeling of separate memory spaces [PoVi10a], modeling of the instrucction cache [CPVM10] and cache level-2 [RPV10]. main results of the project were published by Springer [PRV11][MFP11][SFP11][SFV11].

The AADL simulation and performance analysis technology developed in SPICES was extended in order to give support to HW/SW co-design compatible with the ASSERT System and SW engineering for Real-Time systems. This activity was funded by the HW/SW Co-Design project. Two were the main objectives of the project. On the one hand, the development and production of a HW/SW co-design framework extending the ASSERT process to incorporate HW/SW co-design [VVR12]. This requires the definition of a consistent methodology for the system HW/SW co-design phase ensuring consistency between HW and SW design and verification. After a comprehensive analysis of the state of the art [VFV11], a prototype version of the HW/SW co-design toolset strongly compatible with the ASSERT approach was built [VVR11]. On the other hand, a case study was defined in order to experiment and validate the HW/SW co-design framework developed. As a result, the AADS tool was extended to AADS-T [VVR12].

The FP7 IP 247999 Complex project had as main technical challenge the development of an innovative, highly efficient and productive design methodology and a holistic framework for iteratively exploring the design space of complex, multi-processing, HW/SW embedded systems. This objective had a strategic dimension, since platform providers, EDA providers and system integrators would benefit from this framework likewise. The R&D activities to be performed in COMPLEX targeted new modeling and specification methodologies by using software like MDA design entry for system design as well as the integration of HW and SW timing and power estimation in efficient virtual system simulation, and also multi-objective design-space exploration under consideration of run-time management for power and performance optimizations. The innovative solutions were fully worked out and their effectiveness assessed and demonstrated within the project [GHHR12]. The contribution of the Microelectronics Engineering Group was based on the experience gained in previous projects towards the development of new specification methodologies in MARTE [FVHV10][PHV10] [FHV10] and the modeling, simulation and HW [HBHR10] and SW [ViPo11][BPFH10][PVDM10]. The specification methodology is SW centric, includes the platform independent model (PIM), the platform description model (PDM), the architectural mappings to be explored leading to the platform-specific models (PSM) as well as the definition of the design space and design restrictions and the modeling of the different environment scenarios [HPPV12a][HPV12][HPPV12b][HPPV12c]. Performance analysis requires the generation from MARTE of the HW platform in IP-XACT [FeVi11][HeVi11][HPVC12] and the integration of the HdS and the application SW. The generation tools [PHV11][HPV11][VVB11][HPV12] produce the executable models required for the performance analysis of the experiments selected by the design-space exploration tool [BPF11][HePe11][Vi13]. Compositional Native Simulation (CNS) allows the performance analysis of different PSMs from a single PIM [PoVi11][ViPo12][Vi13]. The project allowed finishing results in multi-OS simulation [PVRM11][FPV13] the from Medea 2A714 SoftSoC project, adaptivity [HVH11] from the IST 033511 ANDRES project, RTOS modeling and SW timing annotation techniques [PDV12] from the FP7 216693 MULTICUBE project and formalization [PHV12][PHV12b] from the FP7 216807 SATURN project. Project results complete the activities carried out in the HW/SW Co-Design project in co-design methodologies based on components using AADL [AFRV12].

The FP7 288307 Pharaon project had as main technical challenges the efficient design of complex, multi-processing, systems addressing the parallelization of the application code, the SW synthesis and the run-time power management [PVB13][PNP14]. A first result was the definition of an integrated design flow with the specification, simulation, parallelization and synthesis tools [CTP12]. The contribution of the Microelectronics Engineering Group is based on previous experience in order to define a MARTE specification methodology supporting parallelization and the automatic generation of the SW stack in each SMP node [PVP12][PPN12a]. Changing the properties in the communication channels in the MARTE model it is possible to decide the degree of parallelism and segmentation [PPN12b][PPN12c][NPP13]. The main result of the project was the eSSYN tool, able to generate automatically the code to be deployed on each comptational resource from the Platform-Specific Model (PSM) [PPN13a][LLP14]. The lack of a platform-independent programming language requires associating different functional codes to each component mapped to different computational devices (i.e. C/C++ for CPUs and OpenCL for GPUs) [PPN13b]. The tool is able to support several communication and synchronization middleware APIs [NPP14a][PPN15] such as MCAPI [NPP14b], as well as the generation of multiple executables on different computing resources [PPN14].

The FP7 IP 247999 Complex project found a continuation in Contrex. Contrex enables energy efficient and cost aware design through analysis and optimisation of real-time, power, temperature and reliability with regard to application demands at different criticality levels. Contrex integrates model-based design methods that can be customized for different application domains and target platforms. The contribution of the University of Cantabria was in the definition of the modeling and specification methodology. Its application as single-source modeling and design framework requires the integration of the analysis [HPV15a], optimization [PPM15], design space exploration and synthesis tools [HPV15b] in a single environment supported by model-to-text (M2T) generators [HeVi16].

This research area was complemented by the activity carried out in the CICYT projects entitled: "SystemC specification, performance analysis and verification methodologies of embedded systems" [PRO03] and: "Verification and platform implementation of SW/HW embedded systems" [PRO05]. These projects found continuity currently in the CICYT project entitled: "REBECCA - Sistemas Electrónicos Empotrados Confiables para Control de Ciudades bajo Situaciones Atípicas" [PRO04][QCL15].

The Group participated to the Network of Excellence IST 004527 ARTIST2 in the Execution Platforms Cluster. The Group contributed to the MCC'06 [ViHe06] and the survey of programming languages [FeVi08]. Michael González Harbour of the Computers and Real-Time Group is the leader of the contribution of the University of Cantabria to the network.

The experience in design of HW/SW Embedded Systems is used to improve the teaching offer [PoVi12][PHV14][PoVi15].
Activity in the Artemis Technology Platform
The Group has participated in the European Embedded Systems Technology Platform ARTEMIS, since its creation in 2005. Since 2006, Eugenio Villar is the representative of the University of Cantabria in the industrial association of the ARTEMIS Platform,
© Copyright GIM (TEISA-UC)    ¤    All rights reserved.    ¤    Legal TermsE-Mail Webmaster